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U4080B
Voice-Switched Circuit for Handsfree Operation
Description
The voice switched speakerphone integrated circuit, U4080B, incorporates a variety of functions (see below). The versality of the device is further enhanced by the provision of a large number of pins giving access to internal circuit points.
Features
D Operates on telephone lines, integrated reference
voltage regulation
D Output power: 100 mW at a 25- load with peak
limitation
D Linear volume control D Monitoring system for background sound level D Wide operating dynamic range through signal
compression
D Chip select pin for active/standby operation
Block Diagram / Application Circuit
Figure 1. Block diagram and application circuit
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
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Preliminary Information
U4080B
Pin Description
Pin 1 Symbol Function R1 Load resistance. Pin 14 Symbol Function GND1 High current ground pin for the speaker
2
RTG
3 4
TI TO
5
TLI
6
TLO
7
RLI
8
RLO
9
MIC
10
MICO
11
CP1
12
CP2
13
TDI
Provides reference current for the transmit and receive attenuators. Transmit attenuator nominal gain resistor. Transmit channel gain is inversely proportional to the resistance RTG connected to Pin 2. Transmit attenuator input. Input resistance is 5 k Transmit attenuator output. Drives the input of the transmit level detector and the external circuit which drives the telephone line. Transmit level detector input. Sets the detector level. Sensitivity to transmit channel signals increases when the value of the resistor decreases. Transmit level detector output. The external RC-element sets the time the comparator will hold the system in the transmit mode after speech ceases. Receive level detector input. An external resistance connected to the pin sets the detection level. Sensitivity to receive channel signals increases when the resistor decreases. Receive level detector output. RC-element connected at the pin sets the time the comparator will hold the system in the receive mode after the receive signal expires. Microphone amplifier input. Input impedance is 10 k and the bias voltage is approximately equal to VB. Microphone amplifier output. Gain is set internally at 34 dB (50 V/V). RC circuit for holding background noise level. The transmit detector compares the CP1 voltage with the speech signal from CP2. Capacitor for detecting the speech signal for comparison with the background noise held at Pin 11 (CP1). Transmit detector input. The microphone amplifier output is coupled to the TDI pin through an external resistor.
15
SAO
16 17
V+ AGC
18
CS
19 20
SAI VCC
21
VB
22 23
GND2 TDO
24
VCI
25
ACF
amplifier output stage. GND1 voltage should be within 10 mV of the ground voltage of Pin 22. Speaker amplifier output. It will source and sink up to 100 mA when ac coupled to the speaker. Gain is set internally at 34 dB (50 V/V). DC supply. A capacitor from this pin to VB stabilizes the speaker amplifier gain control loop, and additionally controls the attack and decay time of this circuit. The gain control loop limits the speaker amp input to prevent clipping at SAO. The internal resistance at the AGC pin is nominally 110 k. Digital chip select input. Logic O: VCC regulator is enabled when 0.7 V; Logic 1: Standby mode drawing 0.5 mA when 1.6 V Speaker amplifier input. Input impedance is ca. 20 k. Regulated output voltage (5.4 V). It powers all circuits except the speaker amplifier output. This voltage can be used for an external circuit i.e., a microprocessor where a filter capacitor is required. Output voltage. VB is approximately VCC/2 and serves as an analog ground to the speakerphone system. Integrated circuit ground (except for the speaker amplifier). Transmit detector output. An external RC circuit holds the system in the transmit mode during pauses between words or phrases. Volume control input. A variable resistor connected to this pin provides receive mode volume control. Attenuator control filter. A connected capacitor reduces noise transients as the attenuator control switches levels of attenuation.
x
y
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
Pin 26 Symbol Function RECO Receive output attenuator.
27 28
RECI RG
This pin is normally ac coupled to the input of the speaker amplifier (Pin 19 - SAI) Receive input attenuator. Input resistance is nominally 5 k. Resistor connected from Pin 28 to ground determines the nominal gain of the receive attenuator. The receive channel gain is directly proportional to the RG resistance.
Absolute Maximum Ratings
Reference point Pin 22, Tamb = 25C, unless otherwise specified Parameters Supply voltage Pin 16 Digital chip select input voltage Pin 18 Speaker amplifier ground voltage Pin 14 Volume control input voltage Pin 24 Storage temperature range Junction temperature Ambient temperature range Power dissipation Tamb = 60C Symbol V+ V18 V14 V24 Tstg Tj Tamb Ptot Value 14 14 3 VCC - 40 to + 125 125 - 20 to + 60 1.3 Unit V V V C C C W
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 50 Unit K/W
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Preliminary Information
U4080B
Electrical Characteristics
V16 = + 7.5 V, V18 = 0.7 V, figure 1, Tamb = 25C, unless other specified Parameters Supply voltages Supply current V16 = 11 V, V18 = 0.7 V V16 = 11 V, V18 = 1.6 V Regulated output voltage Line regulation (deviation) 6.5 V VI 11 V Output resistance ICC = 3 mA Dropout voltage V16 = 5 V Output voltage Output resistance IB = 1.7 mA Attenuators Receive attenuator gain f = 1 kHz, Rmode' V24 = VB V27 = 250 mVrms Gain range R to T modes Idle mode, V27 = 250 Vrms RECO voltage (R mode) Delta RECO voltage RECO sink current (R mode) RECO source current (R mode) RECI input resistance Volume control range (R attenuator gain, R mode) 0.6 VB V24 VB Transmit attenuator gain f = 1 kHz, Tmode' V3 = 250 mVrms Gain range T to R mode Idle mode, V3 = 250 mVrms TO voltage (T mode) Delta TO voltage switch from T to R mode TO sink current, T mode TO source current, T mode TI input resistance Test Conditions / Pins Symbol Min. Typ. Max. Unit
Pin 16 Pin 16 Pin 20
I+ I+ VCC
4.9
5.4 65 6.0 80 2.9 250
9.0 800 5.9 150 20 300 3.3
mA V mV mV V
xx
DVCC
RO VCCSat VB RO
Pin 21 Pin 21
2.5
Pin 26, 27
GR
2.0 40 -20 1.8 75 1.0 3.5
6.0 44 -16 2.3
10 48 -12 3.2 100
dB dB dB V mV
DGR DVRECO
IRECOL IRECOH RRECI GRI VRECO
mA
3.0 5.0 8.0
mA k
x
x
VCR Pins 3 and 4
24.5
22.5
32.5
dB
DGT DVTO
ITOL ITOH RTI GTI VTO
GT
4.0 40 -16.5 1.8
6.0 44 -13 2.3
8.0 48 -8.5 3.2 100
dB dB dB V mV
75 1.0 3.5
mA
5.0 3.0 8.0 mA k
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
Parameters Speaker amplifier Gain, V19 = 20 mVrms Input impedance Output voltage (Pin 19 = cap coupled to GND) High output voltage V19 = 0.1 V, V15 = -100 mA Low output voltage V19 = -0.1 V, V15 = +100 mA Log amplifiers Receive level detector leakage current V8 = VB + 1.0 V Transmit level detector leakage current V6 = VB + 1.0 V Transmit-Receive switching threshold V8/V6 at 20 A to switch T-R comparator Transmit detector DC voltage: Idle mode T mode Distortion R mode: RECI to SAO V27 = 10 mVrms', f = 1 kHz T mode: MIC to TO V9 = 5 mVrms' f = 1 kHz Test Conditions / Pins Pins 15 and 19 Symbol GSA RI VO Min. 33 15 2.4 Typ. 34 22 3.0 Max. 35 37 3.6 Unit dB k V
VOH
5.5
V
VOL
600
mA
Pin 8
ILR
2.0
mA mA
Pin 6 Pins 5 and 7 Pin 25 Pin 23
ILT
2.0
ITH V23 V23
0.8 0 4.0
1.2 V
Pins 15 and 27 d d 1.5 2.0 % %
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Preliminary Information
U4080B
Transmit and Receive Attenuators
The transmit and receive attenuators are supplementary in function. This means that when one is at maximum gain, the other is at maximum attenuation, and vice versa. That is, both are never on or off. They are controlled by the voltage of ACF (attenuator control filter) at Pin 25 being supplied by attenuator control as shown in figure 1 The ACF voltage is provided by the attenuator control block, which receives the three inputs given below: shows the variations versus the ratio of other resistors to R1. RTG affects the gain and attenuation of only the transmit attenuator according to the curves of figure 2, while RG affects only the receive attenuator according to figure 3 Gain difference from on to off, according to the figures, is a reasonably constant 45 dB until the upper gain limit is approached. A value of R1 = 30 k is recommended as a starting point, and then the values of RTG and RG selected to suit the particular design goals. The input impedance of the attenuators (at TI and RECI) is typically 5.0 k, and the maximum input signal which will not cause output distortion is 250 mVrms (707 mVpp). The 4 k resistor and 0.01 F capacitor at RECO (in figure 1) filters out high-frequency components in the receive path. This helps to minimize high-frequency acoustic feedback problems which may occur if the filter were not present. The filter's insertion loss is 1.5 dB at 1.0 kHz. The outputs of the attenuators are inverted from their inputs. Referring to the attenuator control block, the DVACF voltage at its output is determined by three inputs. The relationship of the inputs and outputs is summarized in the following truth table:
D R-T comparator D Transmit detector comparator D Volume control
The response of the attenuators is based on the difference between the ACF voltage and VCC. If the difference (DVACF) is 6 mV, the transmit attenuator is fully on and the receive attenuator is fully off (T mode). If DVACF 150 mV, the circuit is in the R mode. If DVACF 75 mV, the circuit is in the idle mode, and the two attenuators are at gain settings approximately half way (in dB) between their fully on and fully off positions.
[
[
[
Three resistors R1, RTG and RD, determine maximum gain and attenuation values. R1 effects both attenuators according to its value relative to RTG and RG. Figure 4 Transmit T-R Comp Transmit Transmit Receive Receive
20
Det Comp Transmit Idle Transmit Idle
Volume Control No Effect No Effect Affects DVACF Affects DVACF
20
DVACF
Mode Transmit Idle Receive Receive
6.0 mV 75.0 mV 50 - 150 mV 50 - 150 mV
DVRACF = 150 mV
0 dB ) 0 ( dB )
DVTACF = 8 mV
DG R (
DGT DVRACF = 8 mV
-20
20
-40 40 1000 0
94 7863 e
0
94 7864 e
100 RG ( kW )
DVTACF = 150 mV
100 RTG ( kW )
1000
Figure 2.
Figure 3.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
20 GT GR 20 GT
DG T , D G R ( dB )
DG T , D G R ( dB )
0
0
-20
DVRACF = 150 mV
GRT
DVRACF = 8 mV
GTR R1 = 30 kW
-20
-40
-40
GR
-60 0
94 7865 e
100 RTG / R1 or RG / R1
1000
-60 0
94 7866 e
0.2
0.4 VCI
0.6
0.8
1.0
Figure 4.
Figure 5.
20 R
As can be seen from the truth table, the T-R comparator dominates. The transmit detector comparator is effective only in the transmit mode, and the volume control is effective only in the receive mode. The T-R comparator is in the transmit position when the transmit signal present is greater than the receive signal. The transmit detector comparator then determines whether the transmit signal is a result of background noise (a relatively constant signal), or speech, which consists of bursts. If the signal is due to background noise, the attenuators will be put into the idle mode (DVACF = 75 mV). If the signal consists of speech, the attenuators will be switched to the transmit mode (DVACF = 6.0 mV). For further explanation, please refer to the transmit detector circuit (Log. amplifiers). The T-R comparator is in the receive position when there is sufficient receive signal to overcome the background noise AND any speech signals. The DVACF voltage will be 150 mV if the volume control is at the maximum VB', RG and position, i.e. VCI (Pin 24) = VB. If VCI TG will vary in a complementary manner as shown in figure 5 It can be seen that at the minimum recommended operating level (VCI = 0.55 VB) the gain of the transmit attenuator is actually greater than that of the receive attenuator. The effect of varying VCI is to vary DVACF, with a resulting variation in the gains of the attenuators. Figure 6 shows the gain variations with DVACF.
DG T , D G R ( dB )
0
-20
-40
T
-60 0
94 7867 e
40
80
120
160
DVACF ( mV )
Figure 6.
x
A 4.7 F capacitor at Pin 25 smooths the transition between operating modes. This keeps down any "clicks" in the speaker or transmit signal when the ACF voltage switches. The gain separation of the two attenuators can be reduced from the typical 45 dB by connecting a resistor between Pins 20 and 25. The effect is a reduction of voltage in the receive mode, but no effect on the transmit mode voltage. For example, adding a 12 k resistor will reduce DVACF by approximately 15 mV (to 135 mV), decrease the gain of the receive attenuator by approximately 5.0 dB, and increase the gain of the transmit attenuator by a similar amount. If the circuit requires the receive attenuator gain to be +6.0 dB in the receive mode, RG must be adjusted (to 27 k) to re-establish this value. This change will also increase the receive attenuator's gain in the transmit mode by a similar amount. The resistor at TLI may also require changing to reset the sensitivity of the transmit level detector.
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Preliminary Information
U4080B
Log Amplifiers (Transmit and Receive Level Detectors)
The log amplifiers monitor the levels of the transmit and receive signals so as to tell the I-R comparator which mode is in operation. The input signals are applied to the amplifiers (at TLI and RLI) through coupling capacitors and current limiting resistors. The value of these components determines the sensitivity of the respective amplifiers and has an effect on the switching times between transmit and receive modes. The feedback elements for the amplifiers are back-toback diodes which provide a logarithmic gain curve, thus allowing the operation over a wide range of signal levels. The output of the amplifiers are rectified, having a fast rise time and a slow decay time. The rise time (x 1 ms) is determined by the capacitor at Pin 6 (or Pin 8) and an internal 500 resistor. The decay time (x 1 s) is determined by the external RC values at Pin 7. The switching time is not fixed, but depends on the relative values of the transmit and receive signals, as well as these external components. Figure 7 indicates the dc transfer characteristics of the log amps, and figure 8 indicates the transfer characteristics with respect to an ac input signal. The dc level at Pins 5 to 8 is approximately VB.
250 200 150 R = 2.7 kW C = 0.1 mF 100 R = 4.7 kW C = 68 nF
D VO ( mV )
50
Input R C
Log
Output 2.2 MW 2.2 mF
0 0
94 7874 e
20
40 Vi ( mVpp )
60
80
Figure 8.
The T-R comparators responds to the voltages at TLO and RLO, which in turn are functions of the currents sourced out of TLI and RLI, respectively. If an offset at the comparator input is desired (e.g., to prevent noise from switching the system or to give preference to either the transmit or receive channel) it may be achieved by biasing the appropriate input (Pin 5 or 7). A resistor to ground will cause a dc current to flow out of that input, thus forcing the output of that amplifier to be biased slightly higher than normal. This amplifier then becomes the preferred one in the system operation. Resistor values from 500 k to 10 M are recommended for this purpose.
DVO ( mV )
150
Speaker Amplifier
The speaker amplifier has fixed gain of 34 dB and is noninverting. The input impedance is nominally 22 k as long as the output signal is lower than required to activate the peak limiter. Figure 9 shows the typical speaker amplifier output (SAO) swing at Pin 15. Since the output current capability is 100 mA, the lower curve is limited to a 5.0 V swing. The output impedance depends on the output signal level and is relatively low when the signal level is lower than the maximum limits. At 3 VPP the output impedance is 0.5 , and at 4.5 VPP it is 3 . The output is short-circuit protected at approximately 300 mA. When the amplifier is overdriven, the peak limiter causes a portion of the input signal to be shunted to ground in order to maintain a constant output level. The effect is that of a gain reduction caused by a reduction of the input impedance at Pin 19 (SAI) to a value not less than 2 k. The capacitor at Pin 17 (AGC) determines the response time of the peak limiter circuit. When a large input signal is applied to SAI, the voltage at Pin 17 will drop quickly as a current source is applied to the external capacitor.
100
50 0 0
94 7873 e
20
40
60 II ( mA )
80
100
Figure 7.
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x
8 (15)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
When the large input signal is reduced, the current source is turned off, and an internal 110 k resistor discharges the capacitor so the voltage at Pin 17 can return to its normal value of 1.9 V dc. The capacitor also stabilizes the peak limiting feedback loop. If there is a need to mute the speaker amplifier without disabling the rest of the circuit, this may be accomplished by connecting a resistor from Pin 17 to ground. A 100 k resistor will reduce the gain by 34 dB (0 dB from SAI to SAO), and a 10 k resistor will reduce the gain by almost 50 dB. Figure 11 shows the following series of events: 1. CP2 (Pin 12) follows the peaks of the speech signals and decays at a rate determined by the 10 A current source and the capacitor at this pin. 2. CP1 (Pin 11) increases at a rate determined by the RC at this pin after CP has made a positive transition. It will follow the decay pattern of CP2. 3. The non-inverting of the transmit detector comparator follows CP2, gained up by 2.7 and reduced by an offset of 36 mV. This voltage, compared to CP1, determines the output of the comparator. 4. TDO (Pin 23) will rise quickly to 4 V dc in response to a positive transition at CP2, but will decay at a rate determined by the RC at this pin. When TDO is above 3.25 V dc, the circuit will be in the transmit mode. As it decays toward ground, the attenuators are taken to the idle mode.
600
Transmit Detector Circuit
The transmit detector circuit distinguishes speech (which consists of bursts) from the background noise (a relatively constant signal). It does this by storing a voltage level, representative of the average background noise, in the capacitor at CP1 (Pin 11). It has a time constant of approximately 5 seconds (at Pin 11). The voltage at Pin 11 is applied to the inverting input of the transmit detector comparator. In the absence of speech signals, the noninverting input receives the same voltage level minus an offset of 36 mV. In this condition, the output of the comparator will be low, the the voltage at TDO (Pin 23) will be at ground. If the T-R comparator is in the transmit position, the attenuator will be in the idle mode (DVACF = 75 mV). When speech is presented to the microphone, the signal burst appearing at TDI reaches the non-inverting input of the transmit detector comparator before the voltage at the inverting input can change, causing the output to switch high, driving the voltage at TDI up to approximately 4 V. This high level causes the attenuator control block to switch the attenuators from the idle mode to the transmit mode (assuming the T-R comparator is in the transmit mode). As long as the speech continues to arrive and is maintained at a level above the background, the voltage at TDO will be maintained at high level and the circuit will remain in the transmit mode. The time constant of the components at TDO will determine how much time the circuit requires to return to the idle mode after the cessation of microphone speech signals, which occurs during the normal pauses in speech. The series resistor and capacitor at TDI (Pin 13) determine the sensitivity of the transmit detector circuit. Figure 10 indicates the change in dc voltage levels at CP2 and CP1 in response to a steady state sine wave applied at Pin 13 (DVCP1 D 2.7 VCP2). Response time can be reduced by increasing the resistor and decreasing the capacitor value at these pins. The first amplifier (between TDI and CP2) regulates a wide range of input signal levels due to AGC. Figure 7 indicates the dc transfer characteristics of the log amp.
DVCP1
DVCP1 , DVCP2 ( mV )
400
200
DVCP2
0 0 50 100 150 200 250
94 7876 e
VMICO ( mVrms )
Figure 9.
600
DVCP1
DVCP1 , DVCP2 ( mV )
400
200
[
DVCP2
0 0 50 100 150 200 250
94 7876 e
VMICO ( mVrms )
Figure 10.
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
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Preliminary Information
U4080B
Input Signal MIC dV dt CP 2 ( Pin 12 ) DV1 200 mV
[
+ 10CmA [ 2 V sec
2.7 x DV1
Slope 0.5 V / sec CP 1 ( Pin 11 )
[
Non inverting input of transmit 36 mV detector comp
TDO ( Pin 23 ) 4 V
94 7828 e
t
Figure 11. Transmit detector operation
Microphone Amplifier
The microphone amplifier is non-inverting, has an internal gain of 34 dB and a nominal input impedance of 10 k. The output impedance is typically 15 . The maximum voltage swing available is approximately 2 V less than VCC, which is substantially more than what is required in most applications. The input at Pin 9 (MIC) should be ac coupled to the microphone so as not to upset the bias voltage. Generally, microphone sensitivity may be adjusted by varying the two microphone bias resistors rather than an attempting to vary the gain of the amplifier.
x
For stability reasons, supply should be grounded properly against ac noise. If this pin is not well filtered (by a 1000 F capacitor), any variation at V+ caused by the required speaker current flowing through this pin can cause a low frequency oscillation. The result is usually that the circuit will cut the speaker signal on and off at the rate of a few hertz. Experiments have shown that only a few inches of wire between the supply and the IC can cause the problem if the filter capacitor is not physically adjacent to the IC. It is equally imperative that both ground pins (Pins 14 and 22) have a loss connection to the power supply ground.
8
Power Supply (V+)
6
CS = 0
The voltage for the supply at Pin 16 should be in the range of 6.0 to 11V, although the circuit will operate down to 4.0 V. The voltage can be supplied either from Tip and Ring or from a separate supply. The required supply current, with no signal to the speaker, is shown in figure 12 The upper curve indicates the normal operating current when Chip Select (Pin 18) is a logic O. Figure 13 indicates the average dc current required when supplying various power levels to a 25 speaker. Figure 13 also shows the minimum supply voltage required to provide the indicated power levels. The peak in the power supply current at 5.0 to 5.4 V occurs as the VCC circuit comes into regulation.
I 16 ( mA )
4
Select input Tamb = 25 C
2 CS = 1 0 4
94 7877 e
6
8 V16 ( V )
10
12
Figure 12.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
40 100 mW 30 I 16 ( mA ) Tamb = 25 C 30 I S ( mA ) 40 80 mW 50 mW 20 mW 10 5 mW
Tamb = 25 C
20
20
Allowable operating voltage range
10
0 4
94 7878 e
0 6 8 V16 ( V ) 10 12
94 7879 e
4
5
6 V+ ( V )
7
8
Figure 13.
Figure 15.
VCC (Pin 20) is a regulated output voltage of 5.4 V 0.5 V. Regulation will be maintained as long as V+ is (typically) 80 mV greater than the regulated value of VCC. Up to 3 mA can be sourced from this supply for external use. The output impedance is 20 . The 47 F capacitor indicated for connection to Pin 20 is essential for stability reasons. It must be located adjacent to the IC. If the circuit is deselected (see the section on chip select), the VCC voltage will go to 0 V. If the integrated circuit, U4080B, is to be powered from a regulated supply (not the Tip and Ring lines) of less than 6.5 V, the configuration of figure 14 may be used so as to ensure that VCC is regulated. The regulated voltage is applied to both V+ and VCC, with CS held at a logic 1 so as to turn off the internal regulator (the Chip Select function is not available when the circuit is used in this manner). Figure 15 indicates the supply current by this configuration, with no signal at the speaker. When a signal is sent to the speaker the curves of figure 13 apply.
"
VB
VB is a regulated output voltage with a nominal value of 2.9 V 0.4 V. It is derived from VCC and tracks it, holding a value of approximately 54% of VCC. 1.5 mA can be sourced from this supply at a typical output impedance of 250 . The 47 F capacitor indicated for connection to the VB pin is required for stability reasons, and must be adjacent to the IC. If the circuit is deselected (see section on chip select), the VB voltage will go to 0 V.
x
"
Chip Select
The Chip Select pin (Pin 18) allows the chip to be powered down anytime its functions are not required. A logic 1 level in the range of 1.6 to 11 V deselects the chip, and the resulting supply current (at V+) is shown in figure 12 The input resistance at Pin 18 is 75 k. The VCC and the VB regulated voltages go to zero when the chip is deselected. Leaving Pin 18 open is equivalent to a logic O (chip enabled).
y
U 4080 B
22 20 18 16 V+ 200 mF
94 7883 e
Figure 14. Regulated power supply
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
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Preliminary Information
U4080B
Switching time
The switching times of the speakerphone circuit depend not only on the various external components, but also on the operating condition of the circuit at the same time a change is to take effect. For example, the switching time from idle to transmit is generally quicker than the switching time from receive to transmit (or transmit to receive). The components which most significantly affect the timing between the transmit and receive modes are those at Pin 5 (transmit turn-on), Pin 6 (transmit turn-off), Pin 7 (receive turn-on), and Pin 8 (receive turn-off). These four timing functions are not independent, but interact since the T-R comparator operates on a relative T-R comparison, rather than on absolute values. The components at Pins 11, 12, 13 and 23 affect the timing from the transmit to the idle mode. Timing from the idle mode to transmit mode is relatively quick (due to the quick charging of the various capacitors), and is not greatly affected by the component values. Pins 5-8 do not affect the idle-to-transmit timing since the T-R comparator must already be in the transmit mode for this to occur. Additionally, the following should be noted: 1. The RC circuits at Pins 5 and 7 have dual function in that they affect the sensitivity of the respective log amplifiers or in other words, how loud the speech must be in order to gain control of the speakerphone circuit. 2. The RC circuit at Pin 13 also has a dual function in that it determines the sensitivity of the transmit detector circuit. 3. The volume control affects the switching speed and the relative response to transmit signals in the following manner: When the circuit is in the receive mode, reducing the volume control setting increases the signal at TO, and consequently the signal to the TLI pin. Therefore, a given signal at TI will switch the circuit into the transmit mode quicker at low volume settings.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
Application
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
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Preliminary Information
U4080B
Dimensions in mm
Package: DIP 28
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Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 20-May-96
U4080B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
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Preliminary Information

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